Flip-Flops

Flip-flops are bistable logic devices. The circuit illustrated is formed with two cross-coupled NAND gates. The output of each gate is connected to an input of the opposite gate. This produces the regenerative feedback that is characteristic of all flip-flops.

A flip-flop can be triggered into one of two stable states – SET and RESET, where it will remain until switched by the alternate input. This makes them useful as storage devices. SET implies that the Q-output is HIGH. RESET implies that the Q output is LOW. In normal operation, the outputs are always complementary to each other. When Q is HIGH, Q-bar is LOW and vice versa.

Latches – SR Latch

A circuit formed with two cross-coupled NOR gates has two inputs, SET and RESET and is called an SR flip-flop, or more precisely an SR latch. The basic difference between latches and flip-flops is the way in which they are changed from one state to the other. A latch is a type of flip-flop without a clock, or it may have a level-sensitive enable gate.

SR latches can be reset by the input combination R = 1, S = 0. Likewise, if R = 0 and S = 1, the latch will be set to Q = 1. If neither input is active, the latch is in the no-change condition and therefore "remembers" its previous state. In this condition Q can be either 0, or 1, depending on the past history of the SR inputs. The input combination SR = 11 is not allowed.

S-bar R-bar Latch

A circuit formed with two cross-coupled NAND gates is called an S-bar R-bar latch. It is a negative logic version (with active-LOW inputs) of the NOR based SR latch (with active-HIGH inputs).

The logic symbol for S-bar R-bar latch and its corresponding truth table are shown in the diagram. The state SR = 00 is an invalid input combination here and is not allowed. Notice that both SR latches have an invalid input combination.

Applications – Switch Debouncing

When a mechanical switch closes, it physically vibrates or bounces several times before finally making a solid contact. Although these bounces are very short in duration they produce voltage spikes that are often unacceptable in a digital circuit.

An S-bar R-bar latch can be used to eliminate the effect of switch bouncing. When the pole of a switch is not in contact with either outside pin, the latch is in the no-change state. As a result, the first contact with a pin will change output Q (to SET or RESET state). Any further voltage spikes on the same input do not affect the latch. Thus the Q output of the latch provides a clean transition.

Gated SR Latch

A gated SR latch requires an enable input C as shown in the diagram. This circuit arrangement is level-sensitive. When the enable C is HIGH, the latch is said to be transparent. As long as C remains HIGH, the Q output is controlled by the state of the S and R inputs. When C is LOW the Q output remains in its last value. An invalid state occurs when both S and R are HIGH.

The figure shows the logic symbol for an SR latch and its waveforms. The labels 1S and 1R indicate the inputs' dependency on the enable input C and distinguish them from independent, asynchronous S and R inputs.

D Latch

A D latch has only one input in addition to the enable input C. This input is called the D (data) input. The output Q follows the D input when the enable C is HIGH (the latch is transparent for data to move from D to Q). Information present at data input D is transferred to the output Q as long as the enable remains HIGH. Any changes in D when C is LOW will have no effect on the output Q. Thus C = LOW is the no-change state, or memory.

These latches are ideally suited for use as temporary storage for binary information passed between processing units and input/output or indicator units.

Edge-Triggered Flip-Flops

Flip-flops are synchronous bistable devices. The term synchronous means that the output changes state only when a clock input (designated as control input C) is triggered.

Edge-triggered flip-flops change state at either a positive edge (rising edge) or at a negative edge (falling edge) of the clock pulse on the control input. The three basic types are shown in the diagram. The SR, JK and D inputs are called synchronous inputs because data on these inputs can only be transferred to the flip-flop's output on the triggering edge of the clock pulse.

Edge-Triggered SR Flip-Flop

The basic operation of a positive-edge SR flip-flop is shown in the diagram along with its truth table. This type of flip-flop can change state only on the triggering edge of the clock pulse.

When S is HIGH and R is LOW, the output Q goes HIGH and the flip-flop is SET. When S is LOW and R is HIGH, the Q output goes LOW and the flip-flop is RESET. If both S and R are LOW, the output does not change. The diagram shows the waveforms, assuming that Q is initially LOW.

Note that the S and R inputs can be changed at any time when the clock input is LOW or HIGH (except for a very short interval either side of the triggering transition of the clock).

Positive Edge-Triggered JK Flip-Flop

The JK flip-flop is a widely used type of flip-flop. The JK flip-flop works in a very similar way to an SR flip-flop. The only difference is that this flip-flop has NO invalid state. The outputs toggle (change to the opposite state) when both J and K inputs are HIGH.

The basic operation of a positive edge-triggered flip-flop is shown in the diagram along with its truth table. The waveforms given assume that the flip-flop is initially LOW.

Negative Edge-Triggered JK Flip-Flop

The operation and truth table for a negative edge-triggered flip-flop are the same as those for one reacting to a positive trigger except that the falling edge of the clock pulse is the triggering edge.

The diagram shows the waveforms, assuming that the flip-flop is initially RESET.

Edge-Triggered D Flip-Flop

A D flip-flop has only one input in addition to the clock. It is very useful when a single data bit (0 or 1) is to be stored.

The operation of a D flip-flop is much simpler. If there is a HIGH on the D input when a clock pulse is applied, the flip-flop SETs and stores a 1. If there is a LOW on the D input when a clock pulse is applied, the flip-flop RESETs and stores a 0.

The diagram shows the waveforms, assuming that the flip-flop is initially LOW.

Asynchronous Preset and Clear Inputs

Most integrated circuit flip-flops also have asynchronous inputs. They are inputs that affect the state of the flip-flop independently of the clock. They are normally labelled preset (PRE) and clear (CLR). An active level on the reset input will SET the flip-flop and an active level on the clear input will RESET it.

The diagram shows a JK flip-flop with active-LOW preset and clear inputs as indicated by the bubbles. Notice that each time a LOW is applied to these inputs, a flip-flop is SET or RESET regardless of the state of other inputs. In this case, for the synchronous operations to work properly, these asynchronous inputs must both be kept HIGH.

Pulse-Triggered Flip-Flop

The truth tables for pulse-triggered flip-flops are the same as those for edge-triggered flip-flops except for the way they are clocked. Data can be entered into the flip-flop on the rising edge of the clock pulse, but the output does not reflect the input state until the falling edge of the clock pulse. The pulse-triggered flip-flop does not allow data to change while the clock pulse is active.

This type of flip-flop is composed of two sections – the master and the slave. The slave section is clocked on the inverted clock pulse and is controlled by the outputs of the master section rather than by the external inputs.

Registers

A flip-flop is a bistable logic circuit that can store only one bit at a time, either a 1 or a 0. A common requirement in digital systems is to store several bits of data simultaneously.

A register is formed by combining several flip-flops that can store groups of bits. Input bits are entered simultaneously and are stored at the time of a clock edge. The data will then be available at the output pins of the register until the next clock edge occurs.

D flip-flops are appropriate devices for implementing storage registers. Each of the four parallel data lines (for a 4-bit register) is connected to the D input of a flip-flop. The clock inputs of all flip-flops are connected together so that each flip-flop is triggered by the same clock pulse.

Example Application

A typical example of using a register as a temporary storage device is shown by the simple representation of a calculator circuit in the diagram. If a key from a keyboard is pressed and held, the binary sequence of a digit appears at the decoder input and the corresponding decimal digit will appear on the LED display. After the key is released, the digit will disappear from the LED display.

In order to hold the digit after releasing the key, the binary code at the decoder input should be stored. When a 4-bit register is used, the LED display will continue to show the last chosen digit after release of the key because the binary information is stored temporarily.

Frequency Dividers

Another important application of a flip-flop is dividing the frequency of a periodic signal. This operation is used in digital clocks, in frequency meters, oscilloscopes etc.

A single JK flip-flop, connected to toggle (J = K = 1), can be applied as a divide-by-2 frequency divider. The flip-flop changes state at the positive clock edge. The output Q then switches with a period twice that of the clock signal. This results in an output that has one half the frequency of the clock. Further division of the clock frequency can be achieved if the output of one flip-flop is used as the clock input to a subsequent flip-flop. By connecting flip-flops in this way frequency division of 2 n can be realised, where n is the number of flip-flops used.

Counters

JK flip-flops can also be connected together to form a binary counter as shown in the diagram. Both JK flip-flops are initially RESET. The Q output of the first flip-flop clocks the second flip-flop. For each flip-flop, the J and K inputs are tied HIGH.

The flip-flops toggle on the negative edge of the clock. A 2-bit sequence is produced as the flip-flops are clocked. The most significant bit (MSB) of the counter is Q1, and the least significant bit (LSB) is Q0. The flip-flops count in sequence from 0 to 3 (00, 01, 10, 11) and then return to 0 to begin the sequence again. This binary sequence repeats every four clock pulses, as shown in the timing diagram.

Two-Phase Clock Generator

The circuit shown in the diagram generates two clock waveforms that have an alternating sequence of pulses. Each waveform has one-half the frequency of the original clock.

A negative-edge JK flip-flop is connected to toggle (J = K = 1). The signal CLKA is formed by an AND operation between original clock and the Q output of a flip-flop. The AND output CLKA is HIGH only when both its input signals are HIGH. Similarly CLKB is HIGH only when the original clock signal and the Q-bar signal are simultaneously HIGH.