Параметризиран модел на ШИМ

Модел

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity PWM is
Generic ( N : integer);
Port ( clk : in std_logic;
reset : in std_logic;
duty : in std_logic_vector (N-1 downto 0);
pwm : out std_logic);
end PWM;

architecture Behavioral of PWM is
signal cnt : unsigned(N-1 downto 0);
signal pwm_i : std_logic;
signal up: std_logic;
constant CNT_MAX : unsigned(N-1 downto 0) := (others=>’1′);
constant CNT_MIN: unsigned(N-1 downto 0) := (others=>’0′);
begin

pwm_i <= '1' when cnt < unsigned(duty) else '0'; pwm <= pwm_i; counter: process(clk, reset) begin if( reset = '1') then cnt <= (others => ‘0’);
up <= '1'; elsif rising_edge(clk) then if ( up = '1' ) then if( cnt = CNT_MAX ) then up <= '0'; else cnt <= cnt + 1; end if; else if( cnt = CNT_MIN ) then up <= '1'; else cnt <= cnt - 1; end if; end if; end if; end process; end Behavioral; [/code] Тест [code lang="vhdl"] LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY PWM_TB IS END PWM_TB; ARCHITECTURE behavior OF PWM_TB IS --Inputs signal clk : std_logic := '0'; signal reset : std_logic := '0'; signal x : std_logic_vector(3 downto 0) ; --Outputs signal pwm : std_logic; -- Clock period definitions constant clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut:entity work.PWM(Behavioral) Generic map (N => 4)
Port map (
clk => clk,
reset => reset,
duty => x,
pwm => pwm
);

— Clock process definitions
clk_process :process
begin
clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin reset <= '1'; wait for clk_period*2; reset <= '0'; x <= "0100"; wait for clk_period*200; x <= "1010"; wait for clk_period*200; x <= "1111"; wait for clk_period*200; wait; end process; END; [/code] Симулация