Псевдо-Случайни Числа

Литература

http://en.wikipedia.org/wiki/Linear_feedback_shift_register

http://en.wikipedia.org/wiki/Pseudorandom_number_generator

Xilinx Application Note xapp052.pdf

http://www.labbookpages.co.uk/electronics/hwRNG.html

8-битов генератор на псевдо-случайни числа с преместващ регистър

--
-- 8 bit Linear Feedback Shift Register
--
-- see http://www.xilinx.com/support/documentation/application_notes/xapp052.pdf
-- 

library ieee;
use ieee.std_logic_1164.all;

entity lfsr_8 is
    port ( clk : in  std_logic;
           rst : in  std_logic;
           number : out  std_logic_vector (7 downto 0));
end lfsr_8;

architecture behavioral of lfsr_8 is
    signal reg: std_logic_vector(1 to 8); -- numbered after xapp052.pdf
	signal fb: std_logic;
begin
    fb <= reg(4) xnor reg(5) xnor reg(6) xnor reg(8); -- use XNOR to avoid all-zeros dead state
    process (clk, rst) begin
        if rst = '1' then
            reg <= (others => '0');
        elsif rising_edge(clk) then
            reg(1 to 8) <= fb & reg(1 to 7);
        end if;
    end process;
    number<= reg;
end behavioral;

Симулация

16-битов генератор на псевдо-случайни числа с преместващ регистър

--
-- 16 bit Linear Feedback Shift Register
--
-- see http://www.xilinx.com/support/documentation/application_notes/xapp052.pdf
-- 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity lfsr_16 is
    Port ( clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           number : out  STD_LOGIC_VECTOR (15 downto 0));
end lfsr_16;

architecture behavioral of lfsr_16 is
    signal reg: std_logic_vector(1 to 16); -- numbered after xapp052.pdf
	signal fb: std_logic;
begin
    fb <= reg(16) xnor reg(15) xnor reg(13) xnor reg(4); -- use XNOR to avoid all-zeros dead state
    process (clk, rst) begin
        if rst = '1' then
            reg <= (others => '0');
        elsif rising_edge(clk) then
            reg(1 to 16) <= fb & reg(1 to 15);
        end if;
    end process;
    number<= reg;
end behavioral;