Краен Автомат – пример
Диаграма на състоянията

Модел
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity FSM is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
x : out STD_LOGIC;
y : out STD_LOGIC);
end FSM;
architecture Behavioral of FSM is
type StateType is (S0, S1, S2);
signal CurrentState, NextState : StateType;
begin
StateRegister: process(clk, reset)
begin
if(reset = '1')then
CurrentState <= S0;
elsif(rising_edge(clk))then
CurrentState <= NextState;
end if;
end process;
NextStateLogic: process (CurrentState, a, b)
begin
case CurrentState is
when S0 =>
if(a = '1')then
NextState <= S1;
elsif (b = '1')then
NextState <= S2;
else
NextState <= S0;
end if;
when S1 =>
if(a = '1')then
NextState <= S2;
elsif (b = '1')then
NextState <= S0;
else
NextState <= S1;
end if;
when S2 => NextState <= S0;
when others => NextState <= S0;
end case;
end process;
OutputLogic: process (CurrentState) begin
case CurrentState is
when S0 =>
x <= '0';
y <= '1';
when S1 =>
x <= '1';
y <= '1';
when S2 =>
x <= '1';
y <= '0';
when others =>
x <= '0';
y <= '0';
end case;
end process;
end Behavioral;
Симулация

Тест
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY FSM_TB IS
END FSM_TB;
ARCHITECTURE behavior OF FSM_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT FSM
PORT(
a : IN std_logic;
b : IN std_logic;
clk : IN std_logic;
reset : IN std_logic;
x : OUT std_logic;
y : OUT std_logic
);
END COMPONENT;
--Inputs
signal a : std_logic := '0';
signal b : std_logic := '0';
signal clk : std_logic := '0';
signal reset : std_logic := '1';
--Outputs
signal x : std_logic;
signal y : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: FSM PORT MAP (
a => a,
b => b,
clk => clk,
reset => reset,
x => x,
y => y
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 20 ns.
wait for 20 ns;
reset <='0';
wait for clk_period*2;
a <= '1';
b <= '1';
wait for clk_period;
a <= '0';
b <= '0';
wait for clk_period*2;
a <= '1';
wait for clk_period*2;
a <= '0';
b <= '1';
wait for clk_period*2;
wait;
end process;
END;