Преместващи регистри

Необходимите файлове се намират в проекта johnson.

Брояч на Джонсън

• Разгледайте брояча на Джонсън и сответният тест
• Симулирайте го и се уверете, че работи правилно.

• library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity johnson is generic(N: positive); port( clock, reset: in std_logic; reg: out std_logic_vector (N-1 downto 0)); end johnson; architecture v1 of johnson is signal reg_i: std_logic_vector(reg'range); begin reg <= reg_i; process (clock, reset) begin if( reset = '1') then reg_i <= (others=>'0'); elsif rising_edge(clock) then -- using concatenation reg_i <= reg_i(reg'left-1 downto reg'right) &amp;amp; not reg_i(reg'left); end if; end process; end v1; architecture v2 of johnson is signal reg_i: unsigned(reg'range); begin reg <= std_logic_vector(reg_i); process (clock, reset) variable tmp: std_logic; begin if( reset = '1') then reg_i <= (others=>'0'); elsif rising_edge(clock) then -- using shift functions tmp := reg_i(reg'left); reg_i <= shift_left(reg_i, 1); reg_i(reg'right) <= not tmp; end if; end process; end v2;

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  library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;   entity johnson is     generic(N: positive);     port( clock, reset: in std_logic;         reg: out std_logic_vector (N-1 downto 0)); end johnson;   architecture v1 of johnson is     signal reg_i: std_logic_vector(reg'range); begin     reg <= reg_i;     process (clock, reset)     begin         if( reset = '1') then             reg_i <= (others=>'0');         elsif rising_edge(clock) then             -- using concatenation             reg_i <= reg_i(reg'left-1 downto reg'right) &amp;amp; not reg_i(reg'left);         end if;     end process; end v1;   architecture v2 of johnson is     signal reg_i: unsigned(reg'range); begin     reg <= std_logic_vector(reg_i);     process (clock, reset)         variable tmp: std_logic;     begin         if( reset = '1') then             reg_i <= (others=>'0');         elsif rising_edge(clock) then             -- using shift functions             tmp := reg_i(reg'left);             reg_i <= shift_left(reg_i, 1);             reg_i(reg'right) <= not tmp;         end if;     end process; end v2;

  Синтезирана схема на 4-битов брояч на Джонсън.

  

  Тест

  library ieee; use ieee.std_logic_1164.all; entity johnson_tb is end johnson_tb; architecture behavior of johnson_tb is constant CLOCK_PERIOD : time := 10 ns; constant WIDTH : positive := 8; signal clock_run : boolean := true; signal clock : std_logic; signal reset : std_logic; signal led : std_logic_vector(WIDTH-1 downto 0); begin UUT: entity work.johnson(v1) generic map( N => WIDTH ) port map ( clock => clock, reset => reset, reg => led ); clock_process :process begin if clock_run then clock <= '0'; wait for CLOCK_PERIOD/2; clock <= '1'; wait for CLOCK_PERIOD/2; else wait; end if; end process; stim_proc: process begin reset <= '1'; wait until falling_edge(clock); assert led = &quot;00000000&quot; report &quot;led != 00000000&quot;; reset <= '0'; wait until falling_edge(clock); assert led = &quot;00000001&quot; report &quot;led != 00000001&quot;; wait until falling_edge(clock); assert led = &quot;00000011&quot; report &quot;led != 00000011&quot;; wait until falling_edge(clock); assert led = &quot;00000111&quot; report &quot;led != 00000111&quot;; wait until falling_edge(clock); assert led = &quot;00001111&quot; report &quot;led != 00001111&quot;; wait until falling_edge(clock); assert led = &quot;00011111&quot; report &quot;led != 00011111&quot;; wait until falling_edge(clock); assert led = &quot;00111111&quot; report &quot;led != 00111111&quot;; wait until falling_edge(clock); assert led = &quot;01111111&quot; report &quot;led != 01111111&quot;; wait until falling_edge(clock); assert led = &quot;11111111&quot; report &quot;led != 11111111&quot;; wait until falling_edge(clock); assert led = &quot;11111110&quot; report &quot;led != 11111110&quot;; wait until falling_edge(clock); assert led = &quot;11111100&quot; report &quot;led != 11111100&quot;; for i in 1 to 6 loop wait until falling_edge(clock); end loop; assert led = &quot;00000000&quot; report &quot;led != 00000000&quot;; for i in 1 to 8 loop wait until falling_edge(clock); end loop; assert led = &quot;11111111&quot; report &quot;led != 11111111&quot;; clock_run <= false; wait; end process; end;

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  library ieee; use ieee.std_logic_1164.all; entity johnson_tb is end johnson_tb; architecture behavior of johnson_tb is       constant CLOCK_PERIOD : time := 10 ns;     constant WIDTH : positive := 8;     signal clock_run : boolean := true;        signal clock : std_logic;     signal reset : std_logic;     signal led : std_logic_vector(WIDTH-1 downto 0); begin    UUT: entity work.johnson(v1)       generic map( N => WIDTH )       port map (          clock => clock,          reset => reset,          reg => led       );       clock_process :process     begin     if clock_run then         clock <= '0';         wait for CLOCK_PERIOD/2;         clock <= '1';         wait for CLOCK_PERIOD/2;     else         wait;     end if;     end process;    stim_proc: process    begin             reset <= '1';       wait until falling_edge(clock);       assert led = &quot;00000000&quot; report &quot;led != 00000000&quot;;              reset <= '0';       wait until falling_edge(clock);       assert led = &quot;00000001&quot; report &quot;led != 00000001&quot;;              wait until falling_edge(clock);       assert led = &quot;00000011&quot; report &quot;led != 00000011&quot;;              wait until falling_edge(clock);       assert led = &quot;00000111&quot; report &quot;led != 00000111&quot;;              wait until falling_edge(clock);       assert led = &quot;00001111&quot; report &quot;led != 00001111&quot;;              wait until falling_edge(clock);       assert led = &quot;00011111&quot; report &quot;led != 00011111&quot;;              wait until falling_edge(clock);       assert led = &quot;00111111&quot; report &quot;led != 00111111&quot;;              wait until falling_edge(clock);       assert led = &quot;01111111&quot; report &quot;led != 01111111&quot;;              wait until falling_edge(clock);       assert led = &quot;11111111&quot; report &quot;led != 11111111&quot;;              wait until falling_edge(clock);       assert led = &quot;11111110&quot; report &quot;led != 11111110&quot;;              wait until falling_edge(clock);       assert led = &quot;11111100&quot; report &quot;led != 11111100&quot;;              for i in 1 to 6 loop          wait until falling_edge(clock);       end loop;       assert led = &quot;00000000&quot; report &quot;led != 00000000&quot;;              for i in 1 to 8 loop          wait until falling_edge(clock);       end loop;       assert led = &quot;11111111&quot; report &quot;led != 11111111&quot;;              clock_run <= false;       wait;    end process; end;

  

  Стрктурен модела за тестване на проектната единица top експерименталната платка.

  library ieee; use ieee.std_logic_1164.all; entity experiment is port ( clock50: in std_logic; reset: in std_logic; led: out std_logic_vector (7 downto 0)); end experiment; architecture structural of experiment is signal clock: std_logic; begin U1: entity work.johnson(v1) generic map (N =&amp;amp;gt; 8) port map( clock =&amp;amp;gt; clock, reset =&amp;amp;gt; reset, reg =&amp;amp;gt; led); U2: entity work.clock_divider generic map (N =&amp;amp;gt; 23) port map( clock_in =&amp;amp;gt; clock50, clock_out =&amp;amp;gt; clock, reset =&amp;amp;gt; reset); end structural;

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  library ieee; use ieee.std_logic_1164.all;   entity experiment is     port ( clock50: in std_logic;            reset: in std_logic;            led: out std_logic_vector (7 downto 0)); end experiment;   architecture structural of experiment is    signal clock: std_logic; begin    U1: entity work.johnson(v1)       generic map (N => 8)       port map(           clock => clock,           reset => reset,           reg => led);    U2: entity work.clock_divider       generic map (N => 23)       port map(           clock_in => clock50,           clock_out => clock,           reset => reset); end structural;

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Бягаща светлина

• Променете броячът на Джонсън от предишната задача, така че да се получи ефект на “бягаща светлина”.
• Модифицирайте теста, така че да съответства на новата спецификация.
• Синтезирайте проекта и се убедете, че работи на макета.

Указания

При reset, инициализирайте преместващия регистър с единица в единият от битовете и нули в останалите:

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Бягаща светлина със смяна на посоката

• Променете моделът от предишната задача, така че да се получи ефект на “бягаща светлина със смяна на посоката” (виж фигурата по-долу).
• Модифицирайте теста, така че да съответства на новата спецификация.
• Синтезирайте проекта и се убедете, че работи на макета.

Указания

Въведете сигнал dir, който да указва посоката на преместване:

В зависимост от стойността на dir, регистърът премества наляво или надясно.
Стойността на dir да се променя когато единицата достигне края на преместващия регистър.